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? intel corporation, 1996 november 1996 order number: 272971-001 product preview 80960jd 3.3 v embedded 32-bit microprocessor ? 3.3 v, 5 v tolerant, version of the 80960jd processor figure 1. 80960jd microprocessor n pin/code compatible with all 80960jx processors n high-performance embedded architecture one instruction/clock execution core clock rate is 2x the bus clock load/store programming model sixteen 32-bit global registers sixteen 32-bit local registers (8 sets) nine addressing modes user/supervisor protection model n two-way set associative instruction cache 80960jd - 4 kbyte programmable cache locking mechanism n direct mapped data cache 80960jd - 2 kbyte write through operation n on-chip stack frame cache seven register sets can be saved automatic allocation on call/return 0-7 frames reserved for high-priority interrupts n on-chip data ram 1 kbyte critical variable storage single-cycle access n 3.3 v supply voltage 5 v tolerant inputs ttl compatible outputs n high bandwidth burst bus 32-bit multiplexed address/data programmable memory configuration selectable 8-, 16-, 32-bit bus widths supports unaligned accesses big or little endian byte ordering n high-speed interrupt controller 31 programmable priorities eight maskable pins plus nmi up to 240 vectors in expanded mode n two on-chip timers independent 32-bit counting clock prescaling by 1, 2, 4 or 8 lnternal interrupt sources n halt mode for low power n ieee 1149.1 (jtag) boundary scan compatibility n packages 132-lead pin grid array (pga) 132-lead plastic quad flat pack (pqfp) pin 1 132 99 66 33 i960 ? i m i ? 19xx m ?19xx a80960jd ng80960jd xxxxxxxxc0 xxxxxxxxc0s
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. *third-party brands and names are the property of their respective owners. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect il 60056-764 or call 1-800-548-4725 ?intel corporation, 1996
contents iii 80960jd 3.3 v embedded 32-bit microprocessor 1.0 purpose .................................................................................................................................................. 1 2.0 80960jd overview ................................................................................................................................ 1 2.1 80960 processor core ........................................................................................................................ 2 2.2 burst bus ............................................................................................................................................ 2 2.3 timer unit ........................................................................................................................................... 3 2.4 priority interrupt controller ................................................................................................................. 3 2.5 instruction set summary .................................................................................................................... 3 2.6 faults and debugging ........................................................................................................................ 3 2.7 low power operation ......................................................................................................................... 3 2.8 test features ..................................................................................................................................... 4 2.9 memory-mapped control registers .................................................................................................... 4 2.10 data types and memory addressing modes ................................................................................... 4 3.0 package information ....................................................................................................................... 6 3.1 pin descriptions .................................................................................................................................. 6 3.1.1 functional pin definitions ........................................................................................................ 6 3.1.2 80960jx 132-lead pga pinout ............................................................................................. 12 3.1.3 80960jx pqfp pinout ........................................................................................................... 16 3.2 package thermal specifications ...................................................................................................... 19 3.3 thermal management accessories .................................................................................................. 21 4.0 electrical specifications ........................................................................................................... 22 4.1 absolute maximum ratings .............................................................................................................. 22 4.2 operating conditions ........................................................................................................................ 22 4.3 connection recommendations ........................................................................................................ 22 4.4 v cc5 pin requirements (v diff ) ........................................................................................................ 23 4.5 vccpll pin requirements .............................................................................................................. 23 4.6 dc specifications ............................................................................................................................. 24 4.7 ac specifications ............................................................................................................................. 26 4.7.1 ac test conditions and derating curves .............................................................................. 29 4.7.2 ac timing waveforms ........................................................................................................... 30 5.0 bus functional waveforms ........................................................................................................ 37 6.0 device identification ...................................................................................................................... 51 7.0 revision history ............................................................................................................................... 53
contents iv figures figure 1. 80960jd microprocessor ................................................................................................................ i figure 2. 80960jd block diagram ................................................................................................................2 figure 3. 132-lead pin grid array bottom view - pins facing up ............................................................. 12 figure 4. 132-lead pin grid array top view - pins facing down .............................................................. 13 figure 5. 132-lead pqfp - top view ......................................................................................................... 16 figure 6. vcc5 current-limiting resistor ................................................................................................... 23 figure 7. vccpll lowpass filter ............................................................................................................... 23 figure 8. ac test load ............................................................................................................................... 29 figure 9. output delay or hold vs. load capacitance ................................................................................ 29 figure 10. clkin waveform ......................................................................................................................... 30 figure 11. output delay waveform for t ov1 ................................................................................................ 30 figure 12. output float waveform for t of ................................................................................................... 31 figure 13. input setup and hold waveform for t is1 and t ih1 ...................................................................... 31 figure 14. input setup and hold waveform for t is2 and t ih2 ...................................................................... 32 figure 15. input setup and hold waveform for t is3 and t ih3 ...................................................................... 32 figure 16. input setup and hold waveform for t is4 and t ih4 ...................................................................... 33 figure 17. relative timings waveform for t lx , t lxl and t lxa .................................................................... 33 figure 18. dt/r and den timings waveform .............................................................................................. 34 figure 19. tck waveform ............................................................................................................................ 34 figure 20. input setup and hold waveforms for t bsis1 and t bsih1 ............................................................. 35 figure 21. output delay and output float waveform for t bsov1 and t bsof1 ............................................ 35 figure 22. output delay and output float waveform for t bsov2 and t bsof2 ............................................. 36 figure 23. input setup and hold waveform for t bsis2 and t bsih2 ............................................................... 36 figure 24. non-burst read and write transactions without wait states, 32-bit bus .................................. 37 figure 25. burst read and write transactions without wait states, 32-bit bus ..........................................38 figure 26. burst write transactions with 2,1,1,1 wait states, 32-bit bus ................................................... 39 figure 27. burst read and write transactions without wait states, 8-bit bus ............................................40 figure 28. burst read and write transactions with 1, 0 wait states and extra tr state on read, 16-bit bus ....................................................................................... 41 figure 29. bus transactions generated by double word read bus request, misaligned one byte from quad word boundary, 32-bit bus, little endian ..............................42 figure 30. hold/holda waveform for bus arbitration ............................................................................. 43 figure 31. cold reset waveform .................................................................................................................. 44 figure 32. warm reset waveform ................................................................................................................ 45 figure 33. entering the once state ............................................................................................................. 46 figure 34. summary of aligned and unaligned accesses (32-bit bus) ........................................................ 49 figure 35. summary of aligned and unaligned accesses (32-bit bus) (continued) .................................... 50 figure 36. 80960jd device identification register .......................................................................................51
contents v tables table 1. 80960jx instruction set ................................................................................................................. 5 table 2. pin description nomenclature ....................................................................................................... 6 table 3. pin description external bus signals ........................................................................................ 7 table 4. pin description processor control signals, test signals and power ..................................... 10 table 5. pin description interrupt unit signals ..................................................................................... 11 table 6. 132-lead pga pinout in signal order .................................................................................... 14 table 7. 132-lead pga pinout in pin order ......................................................................................... 15 table 8. 132-lead pqfp pinout in signal order .................................................................................. 17 table 9. 132-lead pqfp pinout in pin order ....................................................................................... 18 table 10. 132-lead pga package thermal characteristics ....................................................................... 19 table 11. 132-lead pqfp package thermal characteristics ..................................................................... 20 table 12. maximum t a at various airflows in c ......................................................................................... 21 table 13. 80960jd operating conditions .................................................................................................... 22 table 14. 80960jd dc characteristics ....................................................................................................... 24 table 15. 80960jd icc characteristics ...................................................................................................... 25 table 16. 80960jd ac characteristics ........................................................................................................ 26 table 17. note definitions for table 16, 80960jd ac characteristics (pg. 26) ........................................... 28 table 18. natural boundaries for load and store accesses ....................................................................... 47 table 19. summary of byte load and store accesses ............................................................................... 47 table 20. summary of short word load and store accesses .................................................................... 47 table 21. summary of n-word load and store accesses (n = 1, 2, 3, 4) ................................................... 48 table 22. 80960jd66 die and stepping reference .................................................................................... 51 table 23. fields of 80960jd device id ....................................................................................................... 52 table 24. 80960jd device id model types ................................................................................................ 52 table 25. device id version numbers for different steppings .................................................................... 52

80960jd product preview 1 1.0 purpose this document contains preview information for the 80960jd microprocessor, including electrical characteristics and package pinout information. detailed functional descriptions other than parametric performance are published in the i960 ? jx microprocessor users guide (272483). throughout this data sheet, references to 80960jx indicate features which apply to all of the following: ? 80960ja 5v, 2 kbyte instruction cache, 1 kbyte data cache ? 80l960ja 3.3 v version of the 80960ja ? 80960jd 5v, 4 kbyte instruction cache, 2 kbyte data cache and clock doubling ? 80960jd 3.3v, 5v tolerant version of the 80960jd ? 80960jf 5v, 4 kbyte instruction cache, 2 kbyte data cache ? 80l960jf 3.3 v version of the 80960jf 2.0 80960jd overview the 80960jd offers high performance to cost- sensitive 32-bit embedded applications. the 80960jd is object code compatible with the 80960 core architecture and is capable of sustained execution at the rate of one instruction per clock. this processors features include generous instruction cache, data cache and data ram. it also boasts a fast interrupt mechanism, dual program- mable timer units and new instructions. the 80960jds clock doubler operates the processor core at twice the bus clock rate to improve execution performance without increasing the complexity of board designs. memory subsystems for cost-sensitive embedded applications often impose substantial wait state penalties. the 80960jd integrates considerable storage resources on-chip to decouple cpu execution from the external bus. the 80960jd rapidly allocates and deallocates local register sets during context switches. the processor needs to flush a register set to the stack only when it saves more than seven sets to its local register cache. a 32-bit multiplexed burst bus provides a high-speed interface to system memory and i/o. a full complement of control signals simplifies the connection of the 80960jd to external components. the user programs physical and logical memory attributes through memory-mapped control registers (mmrs) an extension not found on the i960 kx, sx or cx processors. physical and logical configu- ration registers enable the processor to operate with all combinations of bus width and data object alignment. the processor supports a homogeneous byte ordering model. this processor integrates two important peripherals: a timer unit and an interrupt controller. these and other hardware resources are programmed through memory-mapped control registers, an extension to the familiar 80960 architecture. the timer unit (tu) offers two independent 32-bit timers for use as real-time system clocks and general-purpose system timing. these operate in either single-shot or auto-reload mode and can generate interrupts. the interrupt controller unit (icu) provides a flexible means for requesting interrupts. the icu provides full programmability of up to 240 interrupt sources into 31 priority levels. the icu takes advantage of a cached priority table and optional routine caching to minimize interrupt latency. clock doubling reduces interrupt latency by 40% compared to the 80960ja/jf. local registers may be dedicated to high-priority interrupts to further reduce latency. acting independently from the core, the icu compares the priorities of posted interrupts with the current process priority, off-loading this task from the core. the icu also supports the integrated timer interrupts. the 80960jd features a halt mode designed to support applications where low power consumption is critical. the halt instruction shuts down instruction execution, resulting in a power savings of up to 90 percent. the 80960jds testability features, including once (on-circuit emulation) mode and boundary scan (jtag), provide a powerful environment for design debug and fault diagnosis. the solutions960? program features a wide variety of development tools which support the i960 processor family. many of these tools are developed by partner companies; some are developed by intel, such as profile-driven optimizing compilers. for more information on these products, contact your local intel representative.
80960jd 2 product preview figure 2. 80960jd block diagram programmable bus control unit interrupt controller control address/ instruction sequencer physical region configuration interrupt port 1k byte data ram memory interface execution multiply unit divide unit memory-mapped register interface data bus global / local register file src2 dest src1 address control effective constants generation unit address 32-bit address 32-bit data bus request queues and two 32-bit timers 8-set local register cache src1 src2 dest pll, clocks, power mgmt boundary scan controller tap 5 clkin 128 src1 src2 dest src1 dest 9 32 32-bit buses address / data 3 independent 32-bit src1, src2, and dest buses 21 4 kbyte instruction cache two-way set associative 2 kbyte direct mapped data cache 2.1 80960 processor core the 80960jx family is a scalar implementation of the 80960 core architecture. intel designed this processor core as a very high performance device that is also cost-effective. factors that contribute to the cores performance include: ? core operates at twice the bus speed (80960jd only) ? single-clock execution of most instructions ? independent multiply/divide unit ? efficient instruction pipeline minimizes pipeline break latency ? register and resource scoreboarding allow overlapped instruction execution ? 128-bit register bus speeds local register caching ? 4 kbyte two-way set associative, integrated instruction cache ? 2 kbyte direct-mapped, integrated data cache ? 1 kbyte integrated data ram delivers zero wait state program data 2.2 burst bus a 32-bit high-performance bus controller interfaces the 80960jd to external memory and peripherals. the bcu fetches instructions and transfers data at the rate of up to four 32-bit words per six clock cycles. the external address/data bus is multi- plexed. users may configure the 80960jds bus controller to match an applications fundamental memory organi- zation. physical bus width is register-programmed for up to eight regions. byte ordering and data caching are programmed through a group of logical memory templates and a defaults register.
80960jd product preview 3 the bcus features include: ? multiplexed external bus to minimize pin count ? 32-, 16- and 8-bit bus widths to simplify i/o interfaces ? external ready control for address-to-data, data-to- data and data-to-next-address wait state types ? support for big or little endian byte ordering to facilitate the porting of existing program code ? unaligned bus accesses performed transparently ? three-deep load/store queue to decouple the bus from the core upon reset, the 80960jd conducts an internal self test. then, before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the initialization boot record (ibr). the user may examine the contents of the caches at any time by executing special cache control instruc- tions. 2.3 timer unit the timer unit (tu) contains two independent 32-bit timers which are capable of counting at several clock rates and generating interrupts. each is programmed by use of the tu registers. these memory-mapped registers are addressable on 32-bit boundaries. the timers have a single-shot mode and auto-reload capabilities for continuous operation. each timer has an independent interrupt request to the 80960jds interrupt controller. the tu can generate a fault when unauthorized writes from user mode are detected. clock prescaling is supported. 2.4 priority interrupt controller a programmable interrupt controller manages up to 240 external sources through an 8-bit external interrupt port. alternatively, the interrupt inputs may be configured for individual edge- or level-triggered inputs. the interrupt unit (iu) also accepts interrupts from the two on-chip timer channels and a single non-maskable interrupt (nmi ) pin. interrupts are serviced according to their priority levels relative to the current process priority. low interrupt latency is critical to many embedded applications. as part of its highly flexible interrupt mechanism, the 80960jd exploits several techniques to minimize latency: ? interrupt vectors and interrupt handler routines can be reserved on-chip ? register frames for high-priority interrupt handlers can be cached on-chip ? the interrupt stack can be placed in cacheable memory space ? interrupt microcode executes at twice the bus frequency 2.5 instruction set summary the 80960jx adds several new instructions to the i960 core architecture. the new instructions are: ? conditional move ? conditional add ? conditional subtract ?byte swap ?halt ? cache control ? interrupt control table 1 identifies the instructions that the 80960jx supports. refer to i960 ? jx microprocessor users guide (272483) for a detailed description of each instruction. 2.6 faults and debugging the 80960jx employs a comprehensive fault model. the processor responds to faults by making implicit calls to a fault handling routine. specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately. the processor also has built-in debug capabilities. in software, the 80960jx may be configured to detect as many as seven different trace event types. alter- natively, mark and fmark instructions can generate trace events explicitly in the instruction stream. hardware breakpoint registers are also available to trap on execution and data addresses. 2.7 low power operation intel fabricates the 80960jx using an advanced sub- micron manufacturing process. the processors sub- micron topology provides the circuit density for optimal cache size and high operating speeds while
80960jd 4 product preview dissipating modest power. the processor also uses dynamic power management to turn off clocks to unused circuits. users may program the 80960jx to enter halt mode for maximum power savings. in halt mode, the processor core stops completely while the integrated peripherals continue to function, reducing overall power requirements up to 90 percent. processor execution resumes from internally or externally generated interrupts. 2.8 test features the 80960jx incorporates numerous features which enhance the users ability to test both the processor and the system to which it is attached. these features include once (on-circuit emulation) mode and boundary scan (jtag). the 80960jx provides testability features compatible with ieee standard test access port and boundary scan architecture (ieee std. 1149.1). one of the boundary scan instructions, highz, forces the processor to float all its output pins (once mode). once mode can also be initiated at reset without using the boundary scan mechanism. once mode is useful for board-level testing. this feature allows a mounted 80960jd to electrically remove itself from a circuit board. this allows for system-level testing where a remote tester such as an in-circuit emulator can exercise the processor system. the provided test logic does not interfere with component or circuit board behavior and ensures that components function correctly, connections between various components are correct, and various components interact correctly on the printed circuit board. the jtag boundary scan feature is an attractive alternative to conventional bed-of-nails testing. it can examine connections which might otherwise be inaccessible to a test system. 2.9 memory-mapped control registers the 80960jd, though compliant with i960 series processor core, has the added advantage of memory-mapped, internal control registers not found on the i960 kx, sx or cx processors. these give software the interface to easily read and modify internal control registers. each of these registers is accessed as a memory- mapped, 32-bit register. access is accomplished through regular memory-format instructions. the processor ensures that these accesses do not generate external bus cycles. 2.10 data types and memory addressing modes as with all i960 family processors, the 80960jx instruction set supports several data types and formats: ?bit ?bit fields ? integer (8-, 16-, 32-, 64-bit) ? ordinal (8-, 16-, 32-, 64-bit unsigned integers) ? triple word (96 bits) ? quad word (128 bits) the 80960jx provides a full set of addressing modes for c and assembly programming: ? two absolute modes ? five register indirect modes ? index with displacement ? ip with displacement
80960jd product preview 5 table 1. 80960jx instruction set data movement arithmetic logical bit, bit field and byte load store move *conditional select load address add subtract multiply divide remainder modulo shift extended shift extended multiply extended divide add with carry subtract with carry *conditional add *conditional subtract rotate and not and and not or exclusive or not or or not nor exclusive nor not nand set bit clear bit not bit alter bit scan for bit span over bit extract modify scan byte for equal *byte swap comparison branch call/return fault compare conditional compare compare and increment compare and decrement test condition code check bit unconditional branch conditional branch compare and branch call call extended call system return branch and link conditional fault synchronize faults debug processor management atomic modify trace controls mark force mark flush local registers modify arithmetic controls modify process controls *halt system control *cache control *interrupt control atomic add atomic modify notes: asterisk (*) denotes new 80960jx instructions unavailable on 80960ca/cf, 80960ka/kb and 80960sa/sb implementations.
80960jd 6 product preview 3.0 package information the 80960jd is offered with three speeds and two package types. the 132-pin pin grid array (pga) device is specified for operation at v cc =3.3v5% over a case temperature range of 0 to 100c: ? a80960jd-66 (66 mhz core, 33 mhz bus) ? a80960jd-50 (50 mhz core, 25 mhz bus) ? a80960jd-40 (40 mhz core, 20 mhz bus) the 132-pin plastic quad flatpack (pqfp) devices will be specified for operation at v cc = 3.3 v 5% over a case temperature range of 0 to 100c: ? ng80960jd-66 (66 mhz core, 33 mhz bus) ? ng80960jd-50 (50 mhz core, 25 mhz bus) ? NG80960JD-40 (40 mhz core, 20 mhz bus) for complete package specifications and infor- mation, refer to intels packaging handbook (240800). 3.1 pin descriptions this section describes the pins for the 80960jd in the 132-pin ceramic pin grid array (pga) package and 132-lead plastic quad flatpack package (pqfp). section 3.1.1, functional pin definitions describes pin function; section 3.1.2, 80960jx 132- lead pga pinout and section 3.1.3, 80960jx pqfp pinout define the signal and pin locations for the supported package types. 3.1.1 functional pin definitions table 2 presents the legend for interpreting the pin descriptions which follow. pins associated with the bus interface are described in table 3. pins associated with basic control and test functions are described in table 4. pins associated with the interrupt unit are described in table 5. table 2. pin description nomenclature symbol description i input pin only. o output pin only. i/o pin can be either an input or output. C pin must be connected as described. s synchronous. inputs must meet setup and hold times relative to clkin for proper operation. s(e) edge sensitive input s(l) level sensitive input a (...) asynchronous. inputs may be asynchronous relative to clkin. a(e) edge sensitive input a(l) level sensitive input r (...) while the processors reset pin is asserted, the pin: r(1) is driven to v cc r(0) is driven to v ss r(q) is a valid output r(x) is driven to unknown state r(h) is pulled up to v cc h (...) while the processor is in the hold state, the pin: h(1) is driven to v cc h(0) is driven to v ss h(q) maintains previous state or continues to be a valid output h(z) floats p (...) while the processor is halted, the pin: p(1) is driven to v cc p(0) is driven to v ss p(q) maintains previous state or continues to be a valid output
80960jd product preview 7 table 3. pin description external bus signals (sheet 1 of 4) name type description ad31:0 i/o s(l) r(x) h(z) p(q) address / data bus carries 32-bit physical addresses and 8-, 16- or 32-bit data to and from memory. during an address ( t a ) cycle, bits 31:2 contain a physical word address (bits 0-1 indicate size; see below). during a data (t d ) cycle, r ead or write data is present on one or more contiguous bytes, comprising ad31:24, ad23:16, ad15:8 and ad7:0. during write operations, unused pins are driven to determinate values. size, which comprises bits 0-1 of the ad lines during a t a cycle, specifies the number of data transfers during the bus transaction. ad1 ad0 bus transfers 0 0 1 transfer 0 1 2 transfers 1 0 3 transfers 1 1 4 transfers when the processor enters halt mode, if the previous bus operation was a: ? write ad31:2 are driven with the last data value on the ad bus. ? read ad31:4 are driven with the last address value on the ad bus; ad3:2 are driven with the value of a3:2 from the last data cycle. typically, ad1:0 reflect the size information of the last bus transaction (either instruction fetch or load/store) that was executed before entering halt mode. ale o r(0) h(z) p(0) address latch enable indicates the transfer of a physical address. ale is asserted during a t a cycle and deasserted before the beginning of the t d state. it is active high and floats to a high impedance state during a hold cycle (t h ). ale o r(1) h(z) p(1) address latch enable indicates the transfer of a physical address. ale is the inverted version of ale. this signal gives the 80960jd a high degree of compatibility with existing 80960kx systems. ads o r(1) h(z) p(1) address strobe indicates a valid address and the start of a new bus access. the processor asserts ads for the entire t a cycle. external bus control logic typically samples ads at the end of the cycle. a3:2 o r(x) h(z) p(q) address3:2 comprise a partial demultiplexed address bus. 32-bit memory accesses: the processor asserts address bits a3:2 during t a . the partial word address increments with each assertion of rdyrcv during a burst. 16-bit memory accesses: the processor asserts address bits a3:1 during t a with a1 driven on the be1 pin. the partial short word address increments with each assertion of rdyrcv during a burst. 8-bit memory accesses: the processor asserts address bits a3:0 during t a , with a1:0 driven on be1:0 . the partial byte address increments with each assertion of rdyrcv during a burst.
80960jd 8 product preview be3:0 o r(1) h(z) p(1) byte enables select which of up to four data bytes on the bus participate in the current bus access. byte enable encoding is dependent on the bus width of the memory region accessed: 32-bit bus: be3 enables data on ad31:24 be2 enables data on ad23:16 be1 enables data on ad15:8 be0 enables data on ad7:0 16-bit bus: be3 becomes byte high enable (enables data on ad15:8) be2 is not used (state is high) be1 becomes address bit 1 (a1) be0 becomes byte low enable (enables data on ad7:0) 8-bit bus: be3 is not used (state is high) be2 is not used (state is high) be1 becomes address bit 1 (a1) be0 becomes address bit 0 (a0) the processor asserts byte enables, byte high enable and byte low enable during t a . since unaligned bus requests are split into separate bus transactions, these signals do not toggle during a burst. they remain active through the last t d cycle. for accesses to 8- and 16-bit memory, the processor asserts the address bits in conjunction with a3:2 described above. width/ hltd1:0 o r(0) h(z) p(1) width/halted signals denote the physical memory attributes for a bus trans- action: width/hltd1 width/hltd0 00 8 bits wide 0 1 16 bits wide 1 0 32 bits wide 1 1 processor halted the processor floats the width/hltd pins whenever it relinquishes the bus in response to a hold request, regardless of prior operating state. d/c o r(x) h(z) p(q) data/code indicates that a bus access is a data access (1) or an instruction access (0). d/c has the same timing as w/r . 0 = instruction access 1 = data access w/r o r(0) h(z) p(q) write/read specifies, during a t a cycle, whether the operation is a write (1) or read (0). it is latched on-chip and remains valid during t d cycles. 0 = read 1 = write dt/r o r(0) h(z) p(q) data transmit / receive indicates the direction of data transfer to and from the address/data bus. it is low during t a and t w /t d cycles for a r ead; it is high during t a and t w /t d cycles for a write. dt/r never changes state when den is asserted. 0 = receive 1 = transmit table 3. pin description external bus signals (sheet 2 of 4) name type description
80960jd product preview 9 den o r(1) h(z) p(1) data enable indicates data transfer cycles during a bus access. den is asserted at the start of the first data cycle in a bus access and deasserted at the end of the last data cycle. den is used with dt/r to provide control for data transceivers connected to the data bus. 0 = data cycle 1 = not data cycle blast o r(1) h(z) p(1) burst last indicates the last transfer in a bus access. blast is asserted in the last data transfer of burst and non-burst accesses. blast remains active as long as wait states are inserted via the rdyrcv pin. blast becomes inactive after the final data transfer in a bus cycle. 0 = last data transfer 1 = not last data transfer rdyrcv i s(l) ready/recover indicates that data on ad lines can be sampled or removed. if rdyrcv is not asserted during a t d cycle, the t d cycle is extended to the next cycle by inserting a wait state (t w ). 0 = sample data 1 = dont sample data the rdyrcv pin has another function during the recovery (t r ) state. the processor continues to insert additional recovery states until it samples the pin high. this function gives slow external devices more time to float their buffers before the processor begins to drive address again. 0 = insert wait states 1 = recovery complete lock / once i/o s(l) r(h) h(z) p(1) bus lock indicates that an atomic read-modify-write operation is in progress. the lock output is asserted in the first clock of an atomic operation and deasserted in the last data transfer of the sequence. the processor does not grant holda while it is asserting lock . this prevents external agents from accessing memory involved in semaphore operations. 0 = atomic read-modify-write in progress 1 = atomic read-modify-write not in progress once mode: the processor samples the once input during reset. if it is asserted low at the end of reset, the processor enters once mode. in once mode, the processor stops all clocks and floats all output pins. the pin has a weak internal pullup which is active during reset to ensure normal operation when the pin is left unconnected. 0 = once mode enabled 1 = once mode not enabled hold i s(l) hold : a request from an external bus master to acquire the bus. when the processor receives hold and grants bus control to another master, it asserts holda, floats the address/data and control lines and enters the t h state. when hold is deasserted, the processor deasserts holda and enters either the t i or t a state, resuming control of the address/data and control lines. 0 = no hold request 1 = hold request table 3. pin description external bus signals (sheet 3 of 4) name type description
80960jd 10 product preview holda o r(q) h(1) p(q) hold acknowledge indicates to an external bus master that the processor has relinquished control of the bus. the processor can grant hold requests and enter the t h state during reset and while halted as well as during regular operation. 0 = hold not acknowledged 1 = hold acknowledged bstat o r(0) h(q) p(0) bus status indicates that the processor may soon stall unless it has sufficient access to the bus; see i960 ? jx microprocessor users guide (272483). arbitration logic can examine this signal to determine when an external bus master should acquire/relinquish the bus. 0 = no potential stall 1 = potential stall table 4. pin description processor control signals, test signals and power (sheet 1 of 2) name type description clkin i clock input provides the processors fundamental time base; both the processor core and the external bus run at the clkin rate. all input and output timings are specified relative to a rising clkin edge. reset i a(l) reset initializes the processor and clears its internal logic. during reset, the processor places the address/data bus and control output pins in their idle (inactive) states. during reset, the input pins are ignored with the exception of lock /once , stest and hold. the reset pin has an internal synchronizer. to ensure predictable processor initial- ization during power up, reset must be asserted a minimum of 10,000 clkin cycles with v cc and clkin stable. on a warm reset, reset should be asserted for a minimum of 15 cycles. stest i s(l) self test enables or disables the processors internal self-test feature at initial- ization. stest is examined at the end of reset. when stest is asserted, the processor performs its internal self-test and the external bus confidence test. when stest is deasserted, the processor performs only the external bus confidence test. 0 = self test disabled 1 = self test enabled fail o r(0) h(q) p(1) fail indicates a failure of the processors built-in self-test performed during initial- ization. fail is asserted immediately upon reset and toggles during self-test to indicate the status of individual tests: ? when self-test passes, the processor deasserts fail and begins operation from user code. ? when self-test fails, the processor asserts fail and then stops executing. 0 = self test failed 1 = self test passed tck i test clock is a cpu input which provides the clocking function for ieee 1149.1 boundary scan testing (jtag). state information and data are clocked into the processor on the rising edge; data is clocked out of the processor on the falling edge. tdi i s(l) test data input is the serial input pin for jtag. tdi is sampled on the rising edge of tck, during the shift-ir and shift-dr states of the test access port. table 3. pin description external bus signals (sheet 4 of 4) name type description
80960jd product preview 11 tdo o r(q) hq) p(q) test data output is the serial output pin for jtag. tdo is driven on the falling edge of tck during the shift-ir and shift-dr states of the test access port. at other times, tdo floats. tdo does not float during once mode. trst i a(l) test reset asynchronously resets the test access port (tap) controller function of ieee 1149.1 boundary scan testing (jtag). when using the boundary scan feature, connect a pulldown resistor between this pin and v ss . if tap is not used, this pin must be connected to v ss ; however, no resistor is required. see section 4.3, connection recommendations (pg. 22). tms i s(l) test mode select is sampled at the rising edge of tck to select the operation of the test logic for ieee 1149.1 boundary scan testing. v cc C power pins intended for external connection to a v cc board plane. v ccpll C pll power is a separate v cc supply pin for the phase lock loop clock generator. it is intended for external connection to the v cc board plane. in noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. v cc5 C 5 v reference voltage input is the reference voltage for the 5 v-tolerant i/o buffers. this signal should be connected to +5 v for use with inputs which exceed 3.3 v. if all inputs are from 3.3 v components, this pin should be connected to 3.3 v. v ss C ground pins intended for external connection to a v ss board plane. nc C no connect pins. do not make any system connections to these pins. table 5. pin description interrupt unit signals name type description xint7:0 i a(e/l) external interrupt pins are used to request interrupt service. the xint7:0 pins can be configured in three modes: dedicated mode : each pin is assigned a dedicated interrupt level. dedicated inputs can be programmed to be level (low) or edge (falling) sensitive. expanded mode : all eight pins act as a vectored interrupt source. the interrupt pins are level sensitive in this mode. mixed mode : the xint7:5 pins act as dedicated sources and the xint4:0 pins act as the five most significant bits of a vectored source. the least significant bits of the vectored source are set to 010 2 internally. unused external interrupt pins should be connected to v cc . nmi i a(e) non-maskable interrupt causes a non-maskable interrupt event to occur. nmi is the highest priority interrupt source and is falling edge-triggered. if nmi is unused, it should be connected to v cc . table 4. pin description processor control signals, test signals and power (sheet 2 of 2) name type description
80960jd 12 product preview 3.1.2 80960jx 132-lead pga pinout figure 3. 132-lead pin grid array bottom view - pins facing up ad6 ad11 ad13 v cc v cc v cc v cc v cc v cc v cc ad18 ad19 ad22 ad25 ad3 ad7 ad10 v ss v ss v ss v ss v ss v ss v ss ad20 ad24 ad26 ad27 ad0 ad4 ad8 ad9 ad12 ad14 ad15 ad16 ad17 ad21 ad23 ad29 ad30 nc ad28 be3 be2 ad31 v ss v cc be1 v ss v cc be0 v ss v cc ale v cc bstat v ss v cc v ss v cc dt/r v ss v cc v cc ad1 v cc v ss v cc v ss nc clkin v ss v ccpll v cc v ss nc v cc rdyrcv v cc reset v cc v ss ad5 ad2 v ss tdi xint0 nc a2 width/ ads a3 xint1 tms xint2 nc stest trst hold nc fail v cc5 blast lock/ holda tck xint3 xint5 xint7 nmi v cc v cc v cc v cc nc nc ale xint6 v ss v ss v ss v ss nc tdo width/ d/c w/r xint4 p n m l k j h g f e d c b a p n m l k j h g f e d c b a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v ss den v ss hltd1 hltd0 once
80960jd product preview 13 figure 4. 132-lead pin grid array top view - pins facing down tms nc nc v cc v cc v cc v cc clkin v cc v cc v cc ad0 ad3 ad6 xint2 tck stest v ss v ss v ss v ss v ss v ss v ss ad1 ad4 ad7 ad11 xint5 xint3 trst tdi reset rdyrcv nc v ccpll nc ad2 ad5 ad10 ad13 ad8 ad9 v ss v cc ad12 v ss v cc ad14 v ss v cc ad15 v ss v cc v cc ad17 v cc ad21 v ss v cc ad23 ad20 ad18 xint7 xint4 nmi xint6 v cc v ss hold v cc v ss nc v cc v ss v cc5 v cc v ss fail nc a2 nc tdo xint0 xint1 nc a3 dt/r width/ ad31 ad27 ad25 ad28 den ads w/r ale width/ blast bstat ale be1 be0 nc ad19 ad24 d/c holda lock/ v cc v cc v cc v cc v cc v cc v cc be2 ad30 v ss v ss v ss v ss v ss v ss be3 ad29 ad26 ad22 p n m l k j h g f e d c b a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p n m l k j h g f e d c b a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ad16 v ss v ss hltd0 v ss hltd1 once i m ?19xx a80960jd xxxxxxxx c0
80960jd 14 product preview table 6. 132-lead pga pinout in signal order signal pin signal pin signal pin signal pin a2 c5 ad31 k3 tdo b4 v ss b9 a3 c4 ads a1 tms a14 v ss d2 ad0 m14 ale g3 trst c12 v ss d13 ad1 l13 ale a3 v cc a6 v ss e2 ad2 k12 be0 h3 v cc a7 v ss e13 ad3 n14 be1 j3 v cc a8 v ss f2 ad4 m13 be2 l1 v cc a9 v ss f13 ad5 l12 be3 l2 v cc d1 v ss g2 ad6 p14 blast c3 v cc d14 v ss g13 ad7 n13 bstat f3 v cc e1 v ss h2 ad8 m12 clkin h14 v cc e14 v ss h13 ad9 m11 d/c b2 v cc f1 v ss j2 ad10 n12 den e3 v cc f14 v ss j13 ad11 p13 dt/r d3 v cc g1 v ss k2 ad12 m10 fail c6 v cc g14 v ss k13 ad13 p12 hold c9 v cc h1 v ss n5 ad14 m9 holda c2 v cc j1 v ss n6 ad15 m8 lock /once c1 v cc j14 v ss n7 ad16 m7 nc a4 v cc k1 v ss n8 ad17 m6 nc a5 v cc k14 v ss n9 ad18 p4 nc b5 v cc l14 v ss n10 ad19 p3 nc b14 v cc p5 v ss n11 ad20 n4 nc c8 v cc p6 w/r b1 ad21 m5 nc c14 v cc p7 width/hltd0 b3 ad22 p2 nc g12 v cc p8 width/hltd1 a2 ad23 m4 nc j12 v cc p9 xint0 c11 ad24 n3 nc m3 v cc p10 xint1 c10 ad25 p1 nmi a10 v cc p11 xint2 a13 ad26 n2 rdyrcv f12 v ccpll h12 xint3 b12 ad27 n1 reset e12 v cc5 c7 xint4 b11 ad28 l3 stest c13 v ss b6 xint5 a12 ad29 m2 tck b13 v ss b7 xint6 b10 ad30 m1 tdi d12 v ss b8 xint7 a11 note: do not connect any external logic to pins marked nc (no connect pins).
80960jd product preview 15 table 7. 132-lead pga pinout in pin order pin signal pin signal pin signal pin signal a1 ads c6 fail h1 v cc m10 ad12 a2 width/hltd1 c7 v cc5 h2 v ss m11 ad9 a3 ale c8 nc h3 be0 m12 ad8 a4 nc c9 hold h12 v ccpll m13 ad4 a5 nc c10 xint1 h13 v ss m14 ad0 a6 v cc c11 xint0 h14 clkin n1 ad27 a7 v cc c12 trst j1 v cc n2 ad26 a8 v cc c13 stest j2 v ss n3 ad24 a9 v cc c14 nc j3 be1 n4 ad20 a10 nmi d1 v cc j12 nc n5 v ss a11 xint7 d2 v ss j13 v ss n6 v ss a12 xint5 d3 dt/r j14 v cc n7 v ss a13 xint2 d12 tdi k1 v cc n8 v ss a14 tms d13 v ss k2 v ss n9 v ss b1 w/r d14 v cc k3 ad31 n10 v ss b2 d/c e1 v cc k12 ad2 n11 v ss b3 width/hltd0 e2 v ss k13 v ss n12 ad10 b4 tdo e3 den k14 v cc n13 ad7 b5 nc e12 reset l1 be2 n14 ad3 b6 v ss e13 v ss l2 be3 p1 ad25 b7 v ss e14 v cc l3 ad28 p2 ad22 b8 v ss f1 v cc l12 ad5 p3 ad19 b9 v ss f2 v ss l13 ad1 p4 ad18 b10 xint6 f3 bstat l14 v cc p5 v cc b11 xint4 f12 rdyrcv m1 ad30 p6 v cc b12 xint3 f13 v ss m2 ad29 p7 v cc b13 tck f14 v cc m3 nc p8 v cc b14 nc g1 v cc m4 ad23 p9 v cc c1 lock /once g2 v ss m5 ad21 p10 v cc c2 holda g3 ale m6 ad17 p11 v cc c3 blast g12 nc m7 ad16 p12 ad13 c4 a3 g13 v ss m8 ad15 p13 ad11 c5 a2 g14 v cc m9 ad14 p14 ad6 note: do not connect any external logic to pins marked nc (no connect pins).
80960jd 16 product preview 3.1.3 80960jx pqfp pinout figure 5. 132-lead pqfp - top view ad8 ad7 ad6 ad5 ad4 v cc (i/o) v ss (i/o) ad3 ad2 ad1 ad0 v cc (i/o) v cc (core) v ss (core) v cc (core) v ss (core) v ccpll v cc (clk) nc nc rdyrcv v ss (core) reset nc stest v cc (i/o) tdi v ss (i/o) ad27 v cc (i/o) v ss (i/o) ad28 ad29 ad30 ad31 v cc (core) v ss (core) v cc (i/o) v ss (i/o) be3 be2 be1 be0 bstat lock /once v cc (i/o) v ss (i/o) v cc (core) v ss (core) ale holda den dt/r v cc (i/o) v ss (i/o) v cc (core) v ss (core) w/r ads d/c blast 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 trst tck tms hold xint0 xint1 xint2 xint3 v cc (i/o) v ss (i/o) xint4 xint5 xint6 xint7 nmi v cc (core) v ss (core) nc nc v cc5 nc nc fail ale tdo v cc (i/o) v ss (i/o) width/hltd1 v cc (core) v ss (core) width/hltd0 a2 a3 ad9 v cc (i/o) ad10 v ss (i/o) v cc (i/o) ad11 v ss (i/o) v cc (core) v ss (core) ad12 ad13 ad14 ad15 v cc (i/o) v ss (i/o) ad16 ad17 ad18 ad19 nc v cc (i/o) ad22 ad25 ad21 ad20 ad24 ad26 ad23 v ss (i/o) v cc (core) v cc (i/o) v ss (core) v ss (i/o) v ss (i/o) clkin v ss (clk) nc v cc (core) i xxxxxxxx c0 m ? 19xx i960 ? ng80960jx
80960jd product preview 17 table 8. 132-lead pqfp pinout in signal order signal pin signal pin signal pin signal pin ad31 60 ale 24 v cc (core) 47 v ss (core) 124 ad30 61 ads 36 v cc (core) 59 v ss (i/o) 10 ad29 62 a3 33 v cc (core) 74 v ss (i/o) 27 ad28 63 a2 32 v cc (core) 92 v ss (i/o) 40 ad27 66 be3 55 v cc (core) 113 v ss (i/o) 48 ad26 68 be2 54 v cc (core) 115 v ss (i/o) 56 ad25 69 be1 53 v cc (core) 123 v ss (i/o) 64 ad24 70 be0 52 v cc (i/o) 9 v ss (i/o) 71 ad23 75 width/hltd1 28 v cc (i/o) 26 v ss (i/o) 79 ad22 76 width/hltd0 31 v cc (i/o) 41 v ss (i/o) 85 ad21 77 d/c 35 v cc (i/o) 49 v ss (i/o) 93 ad20 78 w/r 37 v cc (i/o) 57 v ss (i/o) 97 ad19 81 dt/r 42 v cc (i/o) 65 v ss (i/o) 106 ad18 82 den 43 v cc (i/o) 72 v ss (i/o) 112 ad17 83 blast 34 v cc (i/o) 80 v ss (i/o) 131 ad16 84 rdyrcv 132 v cc (i/o) 86 nc 18 ad15 87 lock /once 50 v cc (i/o) 94 nc 19 ad14 88 hold 4 v cc (i/o) 98 nc 21 ad13 89 holda 44 v cc (i/o) 105 nc 22 ad12 90 bstat 51 v cc (i/o) 111 nc 67 ad11 95 clkin 117 v cc (i/o) 129 nc 121 ad10 96 reset 125 v ccpll 119 nc 122 ad9 99 stest 128 v cc5 20 nc 126 ad8 100 fail 23 v ss (clk) 118 nc 127 ad7 101 tck 2 v ss (core) 17 xint7 14 ad6 102 tdi 130 v ss (core) 30 xint6 13 ad5 103 tdo 25 v ss (core) 38 xint5 12 ad4 104 trst 1v ss (core) 46 xint4 11 ad3 107 tms 3 v ss (core) 58 xint3 8 ad2 108 v cc (clk) 120 v ss (core) 73 xint2 7 ad1 109 v cc (core) 16 v ss (core) 91 xint1 6 ad0 110 v cc (core) 29 v ss (core) 114 xint0 5 ale 45 v cc (core) 39 v ss (core) 116 nmi 15 note: do not connect any external logic to pins marked nc (no connect pins).
80960jd 18 product preview table 9. 132-lead pqfp pinout in pin order pin signal pin signal pin signal pin signal 1trst 34 blast 67 nc 100 ad8 2 tck 35 d/c 68 ad26 101 ad7 3tms36ads 69 ad25 102 ad6 4hold37 w/r 70 ad24 103 ad5 5xint0 38 v ss (core) 71 v ss (i/o) 104 ad4 6xint1 39 v cc (core) 72 v cc (i/o) 105 v cc (i/o) 7xint2 40 v ss (i/o) 73 v ss (core) 106 v ss (i/o) 8xint3 41 v cc (i/o) 74 v cc (core) 107 ad3 9v cc (i/o) 42 dt/r 75 ad23 108 ad2 10 v ss (i/o) 43 den 76 ad22 109 ad1 11 xint4 44 holda 77 ad21 110 ad0 12 xint5 45 ale 78 ad20 111 v cc (i/o) 13 xint6 46 v ss (core) 79 v ss (i/o) 112 v ss (i/o) 14 xint7 47 v cc (core) 80 v cc (i/o) 113 v cc (core) 15 nmi 48 v ss (i/o) 81 ad19 114 v ss (core) 16 v cc (core) 49 v cc (i/o) 82 ad18 115 v cc (core) 17 v ss (core) 50 lock /once 83 ad17 116 v ss (core) 18 nc 51 bstat 84 ad16 117 clkin 19 nc 52 be0 85 v ss (i/o) 118 v ss (clk) 20 v cc5 53 be1 86 v cc (i/o) 119 v ccpll 21 nc 54 be2 87 ad15 120 v cc (clk) 22 nc 55 be3 88 ad14 121 nc 23 fail 56 v ss (i/o) 89 ad13 122 nc 24 ale 57 v cc (i/o) 90 ad12 123 v cc (core) 25 tdo 58 v ss (core) 91 v ss (core) 124 v ss (core) 26 v cc (i/o) 59 v cc (core) 92 v cc (core) 125 reset 27 v ss (i/o)60ad3193v ss (i/o) 126 nc 28 width/hltd1 61 ad30 94 v cc (i/o) 127 nc 29 v cc (core) 62 ad29 95 ad11 128 stest 30 v ss (core) 63 ad28 96 ad10 129 v cc (i/o) 31 width/hltd0 64 v ss (i/o) 97 v ss (i/o) 130 tdi 32 a2 65 v cc (i/o) 98 v cc (i/o) 131 v ss (i/o) 33 a3 66 ad27 99 ad9 132 rdyrcv note: do not connect any external logic to pins marked nc (no connect pins).
product preview 19 80960jd 3.2 package thermal specifications the 80960jd is specified for operation when t c (case temperature) is within the range of 0c to 100c for both pga and pqfp packages. case temperature may be measured in any environment to determine whether the 80960jd is within its specified operating range. the case temperature should be measured at the center of the top surface, opposite the pins. q ca is the thermal resistance from case to ambient. use the following equation to calculate t a , the maximum ambient temperature to conform to a particular case temperature: t a = t c - p ( q ca ) junction temperature (t j ) is commonly used in reliability calculations. t j can be calculated from q jc (thermal resistance from junction to case) using the following equation: t j = t c + p ( q jc ) similarly, if t a is known, the corresponding case temperature (t c ) can be calculated as follows: t c = t a + p ( q ca ) compute p by multiplying i cc from table 14 and v cc . values for q jc and q ca are given in table 10 for the pga package and table 11 for the pqfp package. for high speed operation, the processors q ja may be significantly reduced by adding a heatsink and/or by increasing airflow. table 12 shows the maximum ambient temperature (t a ) permitted without exceeding t c for both pga and pqfp packages. the values are based on typical i cc and v cc of +3.3 v, with a t case of +100c. table 10. 132-lead pga package thermal characteristics thermal resistance c/watt parameter airflow ft./min (m/sec) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.08) q jc (junction-to-case) 0.7 0.7 0.7 0.7 0.7 0.7 q ca (case-to-ambient) (no heatsink) 25 19 14 12 11 10 q ca (case-to-ambient) (omnidirectional heatsink) 1596544 q ca (case-to-ambient) (unidirectional heatsink) 1686544 notes : 1. this table applies to a pga device plugged into a socket or soldered directly into a board. 2. q ja = q jc + q ca 3. q j-cap = 5.6c/w (approx.) (no heatsink) 4. q j-pin = 6.4c/w (inner pins) (approx.) (no heatsink) 5. q j-pin = 6.2c/w (outer pins) (approx.) (no heatsink) 6. q j-cap = 3c/w (approx.) (with heatsink) 7. q j-pin = 3.3c/w (inner pins) (approx.) (with heatsink) 8. q j-pin = 3.3c/w (outer pins) (approx.) (with heatsink) q jc q ja q j-cap q ca q j-pin
80960jd 20 product preview table 11. 132-lead pqfp package thermal characteristics thermal resistance c/watt parameter airflow ft./min (m/sec) 0 (0) 50 (0.25) 100 (0.50) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.08) q jc (junction-to-case) 4.1 4.3 4.3 4.3 4.3 4.7 4.9 5.3 q ca (case-to-ambient -no heatsink) 23 19 18 16 14 11 9 8 notes: 1. this table applies to a pqfp device soldered directly into board. 2. q ja = q jc + q ca 3. q jl = 13c/w (approx.) 4. q jb = 13.5c/w (approx.) q jb q ja q jc q jl q ca
80960jd product preview 21 3.3 thermal management accessories the following is a list of suggested sources for 80960jd thermal solutions. this is neither an endorsement or a warranty of the performance of any of the listed products and/or companies. heatsinks 1. thermalloy, inc. 2021 west valley view lane dallas, tx 75234-8993 (214) 243-4321 fax: (214) 241-4656 2. wakefield engineering 60 audubon road wakefield, ma 01880 (617) 245-5900 3. aavid thermal technologies, inc. one kool path laconia, nh 03247-0400 (603) 528-3400 table 12. maximum t a at various airflows in c airflow-ft/min (m/sec) f clkin (mhz) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.07) pqfp package t a without heatsink 66 50 40 61 70 77 73 79 84 76 82 86 81 86 89 85 88 91 86 90 92 pga package t a without heatsink 66 50 40 58 68 75 68 75 81 76 82 86 80 84 88 81 86 89 83 87 90 t a with omni heatsink 1 66 50 40 75 81 85 85 88 91 90 92 94 92 94 95 93 95 96 93 95 96 t a with uni-directional heatsink 2 66 50 40 73 79 84 86 90 92 90 92 94 92 94 95 93 95 96 93 95 96 1. 0.248 high omnidirectional heatsink (ai alloy 6061, 41mil fin width, 124 mil center-to-center fin spacing) 2. 0.250 high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing)
80960jd 22 product preview 4.0 electrical specifications 4.1 absolute maximum ratings parameter maximum rating storage temperature C65 o c to +150 o c case temperature under bias C65 o c to +110 o c supply voltage wrt. v ss C0.5 v to + 4.6 v voltage on v cc5 wrt. v ss C0.5 v to + 6.5 v voltage on other pins wrt. v ss C0.5 v to v cc + 0.5 v notice: this document contains information on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product becomes available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. warning: stressing the device beyond the absolute maximum ratings may cause perma- nent damage. these are stress ratings only. oper- ation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reli- ability. 4.2 operating conditions table 13. 80960jd operating conditions symbol parameter min max units notes v cc supply voltage 3.15 3.45 v v cc5 input protection bias 3.15 5.5 v (1) f clkin input clock frequency 80960jd-66 80960jd-50 80960jd-40 12 12 12 33.3 25 20 mhz t c operating case temperature (pga and pqfp) 0100 c notes: 1. see section 4.4, v cc5 pin requirements (v diff ) (pg. 23) 4.3 connection recommendations for clean on-chip power distribution, v cc and v ss pins separately feed the devices functional units. power and ground connections must be made to all 80960jd power and ground pins. on the circuit board, every v cc pin should connect to a power plane and every v ss pin should connect to a ground plane. place liberal decoupling capacitance near the 80960jd, since the processor can cause transient power surges. pay special attention to the test reset (trst ) pin. it is essential that the jtag boundary scan test access port (tap) controller initializes to a known state whether it will be used or not. if the jtag boundary scan function will be used, connect a pulldown resistor between the trst pin and v ss . if the jtag boundary scan function will not be used (even for board-level testing), connect the trst pin to v ss . also, do not connect the tdi, tdo, and tck pins if the tap controller will not be used. pins identified as nc must not be connected in the system .
80960jd product preview 23 4.4 v cc5 pin requirements (v diff ) in mixed voltage systems where the processor is powered by 3.3 volts and interfaces with 5 volt components, v cc5 must be connected to 5 volts. this allows proper 5 volt tolerant buffer operation, and prevents damage to the input pins. the voltage differential between the 80960jx v cc5 pin and its 3.3 volt v cc pins must not exceed 2.25 volts. if this requirement is not met, current flow through the pin may exceed the value at which the processor is damaged. instances when the voltage can exceed 2.25 volts is during power up or power down, where one source reaches its level faster than the other, briefly causing an excess voltage differential. another instance is during steady-state operation, where the differential voltage of the regulator (provided a regulator is used) cannot be maintained within 2.25 volts. two methods are possible to prevent this from happening: ? use a regulator that is designed to prevent the voltage differential from exceeding 2.25 volts, or, as shown in figure 6, place a 100 w resistor in series with the v cc5 pin to limit the current through v cc5 . figure 6. v cc5 current-limiting resistor ? if the regulator cannot prevent the 2.25 volt differ- ential, the addition of the resistor is a simple and reliable method for limiting current. the resistor can also prevent damage in the case of a power failure, where the 5 volt supply remains on and the 3.3 volt supply goes to zero. in 3.3 volt only systems where the 80960jx input pins are driven from 3.3 volt logic, connect the v cc5 pin directly to the 3.3 volt v cc plane. +5 v (0.25 v) v cc5 pin 100 w (5%, 0.5 w) symbol parameter min max units notes v diff v cc5 -v cc difference 2.25 v v cc5 input should not exceed v cc by more than 2.25 v during power-up and power-down, or during steady-state operation. 4.5 v ccpll pin requirements to reduce clock jitter on the i960 jx processor, the v ccpll pin for the phase lock loop (pll) circuit is isolated on the pinout. the lowpass filter, as shown in figure 7, reduces noise induced clock jitter and its effects on timing relationships in system designs. the 4.7 f capacitor must be (low esr solid tantalum), the 0.01 f capacitor must be of the type x7r and the node connecting v ccpll must be as short as possible. figure 7. v ccpll lowpass filter 100 v cc (board plane) v ccpll (on i960 jx processors) w (5%, 1/8 w) f_ca078a 0.01 f 4.7f +
80960jd 24 product preview 4.6 dc specifications table 14. 80960jd dc characteristics symbol parameter min typ max units notes v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 v cc5 + 0.3 v v ol output low voltage 0.4 0.2 v v i ol = 3 ma i ol = 100 m a v oh output high voltage 2.4 v cc - 0.2 vi oh = -1 ma i oh = -200 m a v olp output ground bounce tbd v (1,2) c in input capacitance pga pqfp 15 15 pf f clkin = f min (2) c out i/o or output capacitance pga pqfp 15 15 pf f clkin = f min (2) c clk clkin capacitance pga pqfp 15 15 pf f clkin = f min (2) notes: 1. typical is measured with v cc = 3.3 v and temperature = 25 c. 2. not tested.
80960jd product preview 25 table 15. 80960jd i cc characteristics symbol parameter typ max units notes i li1 input leakage current for each pin except tck, tdi, trst and tms 1 m a0 v in v cc i li2 input leakage current for tck, tdi, trst and tms -140 -250 m av in = 0.45v (1) i lo output leakage current 1 m a0.4 v out v cc r pu internal pull-up resistance for once , tms, tdi and trst 20 30 k w i cc active (power supply) 80960jd-66 80960jd-50 80960jd-40 790 600 500 ma (2,3) (2,3) (2,3) i cc active (thermal) 80960jd-66 80960jd-50 80960jd-40 720 540 435 ma (2,4) (2,4) (2,4) i cc test (power modes) reset mode 80960jd-66 80960jd-50 80960jd-40 halt mode 80960jd-66 80960jd-50 80960jd-40 once mode 703 535 430 61 49 41 10 ma (5) (5) (5) (5) (5) (5) (5) i cc 5 current on the v cc5 pin 80960jd-66 80960jd-50 80960jd-40 200 200 200 a (6)
80960jd 26 product preview 4.7 ac specifications the 80960jd ac timings are based upon device characterization. table 16. 80960jd ac characteristics (sheet 1 of 2) symbol parameter min max units notes input clock timings t f clkin frequency 80960jd-66 80960jd-50 80960jd-40 12 12 12 33.3 25 20 mhz t c clkin period 80960jd-66 80960jd-50 80960jd-40 30 40 12 83.3 83.3 83.3 ns t cs clkin period stability 250 ps (1, 2) t ch clkin high time 8 ns measured at 1.5 v (1) t cl clkin low time 8 ns measured at 1.5 v (1) t cr clkin rise time 4 ns 0.8 v to 2.0 v (1) t cf clkin fall time 4 ns 2.0 v to 0.8 v (1) synchronous output timings t ov1 output valid delay, except ale/ale inactive and dt/r for 3.3v input sig- nals. same as above, but for 5.5v input signals. 2.5 2.5 13.5 16.5 ns (3) t ov2 output valid delay, dt/r 0.5t c + 7 0.5t c + 9 ns t of output float delay 2.5 13.5 ns (4) synchronous input timings t is1 input setup to clkin ad31:0, nmi , xint7:0 6ns(5) t ih1 input hold from clkin ad31:0, nmi , xint7:0 1.5 ns (5) t is2 input setup to clkin rdyrcv and hold 6.5 ns (6) t ih2 input hold from clkin rdyrcv and hold 1ns(6) t is3 input setup to clkin reset 7ns(7) t ih3 input hold from clkin reset 2ns(7) t is4 input setup to reset once , stest 7ns(8) t ih4 input hold from reset once , stest 2ns(8) notes: see table 17 on page 28 for note definitions for this table.
80960jd product preview 27 relative output timings t lx address valid to ale/ale inactive 0.5t c - 5 t lxl ale/ale width 0.5t c - 7 ns (9) t lxa address hold from ale/ale inactive equal loading (9) t dxd dt/r valid to den active equal loading (9) boundary scan test signal timings t bsf tck frequency 0.5t f mhz t bsch tck high time 15 ns measured at 1.5 v (1) t bscl tck low time 15 ns measured at 1.5 v (1) t bscr tck rise time 5 ns 0.8 v to 2.0 v (1) t bscf tck fall time 5 ns 2.0 v to 0.8 v (1) t bsis1 input setup to tck tdi, tms 4 ns t bsih1 input hold from tck tdi, tms 6 ns t bsov1 tdo valid delay 3 30 ns (1,10) t bsof1 tdo float delay 3 30 ns (1,10) t bsov2 all outputs (non-test) valid delay 3 30 ns (1,10) t bsof2 all outputs (non-test) float delay 3 30 ns (1,10) t bsis2 input setup to tck all inputs (non-test) 4ns t bsih2 input hold from tck all inputs (non-test) 6ns table 16. 80960jd ac characteristics (sheet 2 of 2) symbol parameter min max units notes notes: see table 17 on page 28 for note definitions for this table.
80960jd 28 product preview table 17. note definitions for table 16, 80960jd ac characteristics (pg. 26) notes: 1. not tested. 2. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power peaking between 500 khz and 1/3 of the clkin frequency. 3. inactive ale/ale refers to the falling edge of ale and the rising edge of ale . for inactive ale/ale timings, refer to relative output timings in this table. 4. a float condition occurs when the output current becomes less than i lo . float delay is not tested, but is designed to be no longer than the valid delay. 5. ad31:0 are synchronous inputs. setup and hold times must be met for proper processor operation. nmi and xint7:0 may be synchronous or asynchronous. meeting setup and hold time guarantees recog- nition at a particular clock edge. for asynchronous operation, nmi and xint7:0 must be asserted for a minimum of two clkin periods to guarantee recognition. 6. rdyrcv and hold are synchronous inputs. setup and hold times must be met for proper processor operation. 7. reset may be synchronous or asynchronous. meeting setup and hold time guarantees recognition at a particular clock edge. 8. once and stest must be stable at the rising edge of reset for proper operation. 9. guaranteed by design. may not be 100% tested. 10. relative to falling edge of tck. 11. worst-case t ov condition occurs on i/o pins when pins transition from a floating high input to driving a low output state. the address/data bus pins encounter this condition between the last access of a read, and the address cycle of a following write. 5 v signals take 3 ns longer to discharge than 3.3 v signals at 50 pf loads.
product preview 29 80960jd 4.7.1 ac test conditions and derating curves the ac specifications in section 4.7, ac specifi- cations are tested with the 50 pf load indicated in figure 8. figure 9 shows how timings vary with load capacitance; figure 11 shows how output rise and fall times vary with load capacitance. figure 8. ac test load output pin c l = 50 pf for all signals c l figure 9. output delay or hold vs. load capacitance ac timings vs. load cap nom + 0 nom + 5 nom + 10 nom + 15 nom + 20 nom + 25 50 100 150 200 250 300 cl (pf) tov (ns) ris ing falling c l (pf) output valid delay (ns) @ 1.5 v capacitance
80960jd 30 product preview 4.7.2 ac timing waveforms figure 10. clkin waveform figure 11. output delay waveform for t ov1 2.0v 1.5v 0.8v t cf t ch t cl t c t cr clkin ad31:0, ale (active), ale (active), ads , a3:2, be3:0, width/hltd1:0, d/ c , w/ r , den , blast , lock , holda, bstat, fail 1.5v 1.5v 1.5v t ov1
80960jd product preview 31 figure 12. output float waveform for t of figure 13. input setup and hold waveform for t is1 and t ih1 1.5v 1.5v t of clkin ad31:0, ale, ale ads , a3:2, be3:0, width/hltd1:0, d/ c , w/ r , dt/ r , den , blast , lock clkin ad31:0 1.5v 1.5v 1.5v t is1 t ih1 1.5v nmi xint7:0 valid
80960jd 32 product preview figure 14. input setup and hold waveform for t is2 and t ih2 figure 15. input setup and hold waveform for t is3 and t ih3 clkin valid hold, 1.5v 1.5v 1.5v 1.5v 1.5v t is2 t ih2 rdyrcv clkin reset 1.5v 1.5v t ih3 t is3
80960jd product preview 33 figure 16. input setup and hold waveform for t is4 and t ih4 figure 17. relative timings waveform for t lx , t lxl and t lxa reset valid once, t is4 t ih4 stest clkin ale 1.5v 1.5v 1.5v ale 1.5v 1.5v ad31:0 valid t lxa t a t w /t d 1.5v valid 1.5v t lxl t lx
80960jd 34 product preview figure 18. dt/r and den timings waveform figure 19. tck waveform clkin dt/ r 1.5v 1.5v 1.5v den valid t dxd t a t w /t d t ov1 t ov2 2.0v 1.5v 0.8v t bsch t bscl t bscf t bscr
80960jd product preview 35 figure 20. input setup and hold waveforms for t bsis1 and t bsih1 figure 21. output delay and output float waveform for t bsov1 and t bsof1 tck tms 1.5v 1.5v 1.5v tdi 1.5v 1.5v valid t bsis1 t bsih1 tck 1.5v 1.5v 1.5v t bsov1 tdo valid t bsof1 1.5v
80960jd 36 product preview figure 22. output delay and output float waveform for t bsov2 and t bsof2 figure 23. input setup and hold waveform for t bsis2 and t bsih2 tck 1.5v 1.5v 1.5v t bsov2 non-test valid t bsof2 outputs 1.5v tck non-test 1.5v 1.5v 1.5v 1.5v 1.5v valid t bsis2 t bsih2 inputs
product preview 37 80960jd 5.0 bus functional waveforms figures 24 through 29 illustrate typical 80960jd bus transactions. figure 30 depicts the bus arbitration sequence. figure 31 illustrates the processor reset sequence from the time power is applied to the device. figure 32 illustrates the processor reset sequence when the processor is in operation. figure 33 illustrates the processor once sequence from the time power is applied to the device. figures 34 and 35 also show accesses on 32-bit buses. tables 18 through 21 summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to data alignment. figure 24. non-burst read and write transactions without wait states, 32-bit bus clkin ad31:0 ale ads a3:2 be3:0 width1:0 d/ c w/ r dt/ r den rdyrcv blast addr d in invalid addr data out 10 10 t a t d t r t i t i t a t d t r t i t i f_jf030a
80960jd 38 product preview figure 25. burst read and write transactions without wait states, 32-bit bus addr d d addr data data data data 1 0 1 0 clkin ad31:0 ale ads a3:2 be3:0 width1:0 d/ c w/ r blast dt/ r den rdyrcv t a t d t d t r t a t d t d t d t d t r in in out out out out 00 or 10 01 or 11 00 01 10 11
80960jd product preview 39 figure 26. burst write transactions with 2,1,1,1 wait states, 32-bit bus addr data 1 0 data data data clkin ad31:0 ale ads a3:2 be3:0 width1:0 d/ c w/ r blast dt/ r den rdyrcv t a t w t w t d t w t d t w t d t w t d t r out out out out f_jf032a 0 0 0 1 1 0 1 1
80960jd 40 product preview figure 27. burst read and write transactions without wait states, 8-bit bus addr d d addr data data data data clkin ad31:0 ale ads a3:2 be1 /a1 width1:0 d/ c w/ r blast dt/ r den rdyrcv t a t d t d t r t a t d t d t d t d t r 00,01,10 or 11 00,01,10 or 11 00 01 10 11 00 00 be0 /a0 in in out out out out f_jf033a 00 or 10 01 or 11
80960jd product preview 41 figure 28. burst read and write transactions with 1, 0 wait states and extra tr state on read, 16-bit bus addr d d addr data data clkin ad31:0 ale ads a3:2 be3 / bhe width1:0 d/ c w/ r blast dt/ r den rdyrcv t w t d t d t r t r t a t w t d t d t r 00,01,10, or 11 00,01,10, or 11 t a be0 / ble be1 /a1 01 01 0 1 01 out out in in f_jf034a
80960jd 42 product preview figure 29. bus transactions generated by double word read bus request, misaligned one byte from quad word boundary, 32-bit bus, little endian t a t d t r t a t d t r t a t d t r t a t d t r clkin ad31:0 ale ads a3:2 be3:0 width1:0 d/ c w/ r blast dt/ r den rdyrcv 00 00 01 10 1 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 valid aa a d a d in in d in d in
80960jd product preview 43 figure 30. hold/holda waveform for bus arbitration clkin valid outputs: ad31:0, ale, ale , ads , a3:2, be3:0, width/hltd1:0, d/ c , w/ r , dt/ r, den , blast , lock hold holda ~ ~ ~ ~ ~ ~ ~ ~ (note) note: hold is sampled on the rising edge of clkin. the processor asserts holda to grant the bus on the same edge in which it recognizes hold if the last state was t i or the last t r of a bus transaction. similarly, valid ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t i or t r t h t h t i or t a the processor deasserts holda on the same edge in which it recognizes the deassertion of hold.
80960jd 44 product preview figure 31. cold reset waveform clkin ale , ads , ale,w/ r , reset lock/ stest v cc dt/ r fail ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ first bus activity ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ valid ~ ~ (output) once ad31:0, a3:2,d/c width/hltd1:0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ (note 1) ~ ~ ~ ~ idle (note 2) hold ~ ~ valid input (note 3) ~ ~ ~ ~ ~ ~ ~ ~ be3:0 , den , blast ~ ~ ~ ~ ~ ~ valid output (note 3) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ holda v 10,000 clkin periods, for pll stabilization. cc and clkin stable to reset high, minimum ~ ~ ~ ~ built-in self-test, approximately 207,000 clkin periods (if selected) (input) ~ ~ 1. the processor asserts fail during built-in self-test. if self- test passes, the fail pin is deasserted.the processor also asserts fail during the bus confidence test. if the bus confidence test passes, fail is deasserted and the processor begins user program execution. notes: 2. if the processor fails built-in self-test, it initiates one dummy load bus access. the load address indicates the point of self-test failure. 3. since the bus is idle, hold requests are honored during reset and built-in self-test. ~ ~ ~ ~
80960jd product preview 45 figure 32. warm reset waveform ~ ~ ~ ~ maximum reset low to reset state 4 clkin cycles ~ ~ ~ ~ ~ ~ clkin ad31:0, a3:2, d/c stest reset ~ ~ ~ ~ reset high to first bus minimum reset low time 15 clkin cycles ~ ~ ~ ~ ~ ~ ~ ~ holda ~ ~ ~ ~ ~ ~ ~ ~ valid ale , ads , be3:0 , den , blast ale, w/ r , dt/ r , bstat, width/hltd1:0 ~ ~ ~ ~ fail ~ ~ ~ ~ ~ ~ hold ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ lock/once ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ activity, 46 clkin cycles ~ ~ ~ ~ ~ ~ ~ ~
80960jd 46 product preview figure 33. entering the once state clkin ale , ads , ale,w/r , reset lock/ v cc dt/r, width/hltd1:0 fail ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ once ad31:0, a3:2, d/c ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ hold ~ ~ ~ ~ ~ ~ be3:0 , den , blast ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ holda ~ ~ ~ ~ (input) minimum 10,000 clkin periods, for pll v cc and clkin stable to reset high, ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ (note 1) 1. once mode may be entered prior to the rising edge of reset: once input is not latched until the rising edge of reset. notes: clkin may not be allowed to float. ~ ~ ~ ~ stest ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 2. the once input may be removed after the processor enters once mode. ~ ~ stabilization. it must be driven high or low or continue to run.
80960jd product preview 47 table 18. natural boundaries for load and store accesses data width natural boundary (bytes) byte 1 short word 2 word 4 double word 8 triple word 16 quad word 16 table 19. summary of byte load and store accesses address offset from natural boundary (in bytes) accesses on 8-bit bus (width1:0=00) accesses on 16 bit bus (width1:0=01) accesses on 32 bit bus (width1:0=10) +0 (aligned) ? byte access ? byte access ? byte access table 20. summary of short word load and store accesses address offset from natural boundary (in bytes) accesses on 8-bit bus (width1:0=00) accesses on 16 bit bus (width1:0=01) accesses on 32 bit bus (width1:0=10) +0 (aligned) ? burst of 2 bytes ? short-word access ? short-word access +1 ? 2 byte accesses ? 2 byte accesses ? 2 byte accesses
80960jd 48 product preview table 21. summary of n -word load and store accesses ( n = 1, 2, 3, 4) address offset from natural boundary in bytes accesses on 8-bit bus (width1:0=00) accesses on 16 bit bus (width1:0=01) accesses on 32 bit bus (width1:0=10) +0 (aligned) ( n =1, 2, 3, 4) ? n burst(s) of 4 bytes ? case n =1: burst of 2 short words ? case n =2: burst of 4 short words ? case n =3: burst of 4 short words burst of 2 short words ? case n =4: 2 bursts of 4 short words ? burst of n word(s) +1 ( n =1, 2, 3, 4) +5 ( n = 2, 3, 4) +9 ( n = 3, 4) +13 ( n = 3, 4) ? byte access ? burst of 2 bytes ? n -1 burst(s) of 4 bytes ? byte access ? byte access ? short-word access ? n -1 burst(s) of 2 short words ? byte access ? byte access ? short-word access ? n -1 word access(es) ? byte access +2 ( n =1, 2, 3, 4) +6 ( n = 2, 3, 4) +10 ( n = 3, 4) +14 ( n = 3, 4) ? burst of 2 bytes ? n -1 burst(s) of 4 bytes ? burst of 2 bytes ? short-word access ? n -1 burst(s) of 2 short words ? short-word access ? short-word access ? n -1 word access(es) ? short-word access +3 ( n =1, 2, 3, 4) +7 ( n = 2, 3, 4) +11 ( n = 3, 4) +15 ( n = 3, 4) ? byte access ? n -1 burst(s) of 4 bytes ? burst of 2 bytes ? byte access ? byte access ? n -1 burst(s) of 2 short words ? short-word access ? byte access ? byte access ? n -1 word access(es) ? short-word access ? byte access +4 ( n = 2, 3, 4) +8 ( n = 3, 4) +12 ( n = 3, 4) ? n burst(s) of 4 bytes ? n burst(s) of 2 short words ? n word access(es)
80960jd product preview 49 figure 34. summary of aligned and unaligned accesses (32-bit bus) 04 812162024 01 234 5 6 one double-word short-word load/store word load/store double-word load/store byte, byte accesses short access (aligned) short access (aligned) byte, byte accesses word access (aligned) byte, short, byte, accesses short, short accesses byte, short, byte accesses byte offset word offset one double-word burst (aligned) byte, short, word, byte accesses short, word, short accesses byte, word, short, byte accesses word, word accesses burst (aligned)
80960jd 50 product preview figure 35. summary of aligned and unaligned accesses (32-bit bus) (continued) 04 812162024 0 123456 triple-word load/store quad-word load/store word, word, word accesses word, accesses word, word, word, word, word, word, word accesses byte offset word offset one three-word burst (aligned) byte, short, word, word, byte accesses short accesses short, word, word, byte, word, word, short, byte accesses word, word, word accesses one four-word burst (aligned) byte, short, word, word, word, byte accesses short, word, word, word, short accesses byte, word, word, word, short, byte accesses accesses word, word word,
product preview 51 80960jd 6.0 device identification 80960jd processors may be identified electrically, according to device type and stepping (see figure 36, and table 22 through table 25). table 22 identifies the device id for all 3.3 v and 5 v, 80960jd processors. figure 36, and table 23 through table 25 identify all 3.3 v, 5 v-tolerant, 80960jd processors. the device id for the c0 stepping is enhanced to differentiate between 3.3 v and 5 v supply voltages, and between non-clock- doubled and clock-doubled cores when stepping from the a2 stepping to the c0 stepping. the 32-bit identifier is accessible in three ways: ? upon reset, the identifier is placed into the g0 register. ? the identifier may be accessed from supervisor mode at any time by reading the device id register at address ff008710h. ? the ieee standard 1149.1 test access port may select the device id register through the idcode instruction. ? the device and stepping letter is also printed on the top side of the product package. table 22. 80960jd die and stepping reference device and stepping version number part number manufacturer x complete id (hex) 80960jd a, a2 0000 1000 1000 0010 0000 0000 0001 001 1 08820013 80960jd c0 0011 0000 1000 0011 0000 0000 0001 001 1 30830013 figure 36. 80960jd device identification register 28 24 20 40 16 12 8 1 1 0 0 1 0 0 0 0 0 0 0 manufacturer id part number version model gen product type v cc 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
80960jd 52 product preview note: this data sheet applies to the 80960jd c0 stepping. table 23. fields of 80960jd device id field value definition version see table 25 indicates major stepping changes. v cc 0 = 3.3 v device 1 = 5v device indicates that a device is 3.3 v or 5.0 v. product type 00 0100 (indicates i960 cpu) designates type of product. generation type 0001 = j-series indicates the generation (or series) of product. model d000c d = clock doubled (0) not clock-doubled (1) clock doubled c = cache size (0) 4k i-cache, 2k d-cache (1) 2k i-cache, 1k d-cache indicates member within a series and specific model information. manufacturer id 000 0000 1001 (indicates intel) manufacturer id assigned by ieee. table 24. 80960jd device id model types device version v cc product gen. model manufacturer id 1 80960jd a, a2 see table 25 1 000100 0001 00000 00000001001 1 80960jd c0 0 000100 0001 10000 00000001001 1 table 25. device id version numbers for different steppings stepping version a0 0000 a2 0000 c0 0011
product preview 53 80960jd 7.0 revision history this is the first revision of the 3.3 v device.

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